Recently, a liquid crystal display (LCD) apparatus, featuring thin thickness, small weight and low power usage, has come into widespread use, as display apparatus, and is used predominantly in a display section of a mobile device, such as mobile phone or cellular phone, PDA (Personal Digital Assistant) or a notebook PC. However, of these days, the technique for forming a liquid crystal display to a large size or for coping with moving pictures has been improved such that realization of a large size display apparatus of a mobile type but also of a desktop type, or a large size liquid crystal television receiver, has become feasible. For liquid crystal display apparatus, a liquid crystal display apparatus of the active matrix driving system, capable of high definition demonstration, is currently in use. Referring first to FIG. 15, a typical structure of the liquid crystal display apparatus of the active matrix driving system is schematically described. Meanwhile, FIG. 15 schematically shows, by an equivalent circuit, an essential structure centered about the connection portion to a single pixel in a liquid crystal display section.
In general, a display 960 of a liquid crystal display apparatus of the active matrix driving system comprises a semiconductor substrate which includes a matrix array of transparent pixel electrodes 964 and thin film transistors (TFTs) 963 (an array of 1280 columns each composed of three pixels and 1024 pixel rows in the case of a color SXGA panel), a opposing substrate, in which a transparent electrode 966 is provided over its entire surface, and a liquid crystal material which is enclosed in a space defined between the semiconductor substrate and the opposing substrate which are mounted facing each other.
The TFTs, having the switching function, are controlled by scanning signals. When the TFTs are turned on, the gray scale voltage, corresponding to a picture signal, is applied to pixel electrode 964. The liquid crystal is changed in transmittance by the potential difference between the pixel electrode 964 and the opposing electrode 966. The potential difference is retained for a predetermined time by a liquid crystal capacitance 965 to display a picture.
On the semiconductor substrate, data lines 962 for delivering plural level voltages (gray scale voltage) to be applied to the respective pixel electrodes 964 and scanning lines 961 for sending scanning signals are arrayed in a lattice configuration. The numbers of the data lines and the scanning lines are 1280×3 and 1024, respectively, for the case of the above color SXGA panel. The scanning lines 961 and the data lines 962 represent large capacitive load due e.g. to the capacitance generated in the intersections and to the liquid crystal capacitance sandwiched between the two facing substrates.
Meanwhile, the scanning signal is supplied by a gate driver 970 to the scanning line 961, while the gray scale voltage is supplied from a data driver 980 to the pixel electrodes 964 over a data line 962.
Data is written from one frame to another within one frame period ( 1/60 sec), that is, data is selected from one pixel row to another, viz. from one scanning line to another, and the gray scale voltage is supplied from each data line during the select period.
While it is only necessary for the gate driver 970 to supply at least binary scanning signal, it is necessary for the data driver 980 to drive the data lines with the gray scale voltage of multiple levels corresponding to the number of gray levels. For this reason, a differential amplifier capable of outputting a high precision voltage is used as a buffer unit of the data driver 980.
Recently, with the tendency towards high picture quality (i.e. towards multiple colors), there is an increasing demand for at least 260000 colors (picture data of 6 bits for each of RGB) and for as many as 26800000 colors (picture data of 8 bits for each of RGB).
Hence, the data driver, outputting the gray scale voltage relating to multi-bit picture data, is required to output the voltages to extremely high accuracy. Moreover, the number of devices of the circuitry processing the picture data is increased, thus leading to an increased chip area of the data driver LSI and to increased cost. This problem will now be discussed in detail.
FIG. 16 is a diagram illustrating the configuration of the data driver 980 of FIG. 15 and, more precisely, shows a block diagram showing essential parts of the data driver 980. Referring to FIG. 16, the data driver 980 comprises a latch address selector 981, a latch 982, a gray scale voltage generating circuit 983, a plural number of decoders 984, and a plural number of buffer circuits 985.
The latch address selector 981 determines the data latch timing, based on a clock signal CLK. At a timing as determined by the latch address selector 981, the latch 982 latches digital picture data and, responsive to an STB signal (strobe signal), unanimously outputs the latched data to the respective decoders 984. The gray scale voltage generating circuit 983 generates a number of gray scale voltages related to the picture data. The decoder 984 selects and outputs one of the gray scale voltages corresponding to the input data. The buffer circuit 985 is supplied with the gray scale voltage output from the decoder 984 to amplify the current to issue an output voltage Vout.
For example, in case of 6-bit picture data being input, the number of gray levels is 64, with the gray scale voltage generating circuit 983 generating 64-level gray scale voltages. The decoder 984 includes a circuit for selecting one gray scale voltage from the 64 level gray scale voltages.
For example, in case of 8-bit picture data being input, the number of gray levels is 256, with the gray scale voltage generating circuit 983 generating 256-level gray scale voltages. The decoder 984 includes a circuit for selecting one gray scale voltage from the 256 level gray scale voltages.
With increase in the number of bits, the gray scale voltage generating circuit 983 or the decoder 984 is increased in circuit scale. For example if the number of bits is increased from 6 to 8, the circuit scale is increased by a factor not less than four. Thus, with increase in the number of bits, the chip area of the data driver LSI is increased to raise the cost.
There is described in Patent Document 1, specified below, a structure for suppressing the chip area of the data driver LSI from increasing, despite increase in the number of bits. An illustrative structure as proposed in the Patent Document 1 is shown in FIG. 17, corresponding to FIG. 16 of the Patent Document 1.
Referring to FIG. 17, this data driver differs from the data driver shown in FIG. 16 as to the structure of a gray scale voltage generating circuit 986, a decoder 987 and a buffer circuit 988. In the data driver, shown in FIG. 17, the gray scale voltage generating circuit 986 generates the gray scale voltage, every two gray levels, to decrease the number of gray level voltage lines of the decoder 987 to approximately one-half that of the decoder 984 of FIG. 16. The decoder 987 selects two gray level voltages, depending on picture data, to send out the selected voltages to the buffer circuit 988, which buffer circuit then is able to apply current amplification to the two gray level voltages and a gray level voltage intermediate between these two gradation voltages to output the resulting voltage.
In the configuration disclosed in the Patent Document 1, provided with the buffer circuit 988, supplied with two gray scale voltages to selectively output one of the two gray scale voltages and the voltage intermediate between the two gradation voltages, it is contemplated to reduce the number of the gray scale voltage lines of the decoder 987 and hence the circuit scale of the decoder 987 to save the floor and hence the production cost.
In Patent Documents 2 and 3, as specified below, there is described a structure for significantly saving the data recording area of a circuit for converting multi-bit digital signals into analog signals (digital-to-analog converter, abbreviated to DAC), as an interpolation DAC. The technique disclosed in Patent Document 3 is an improvement over that of the Patent Document 2 and is relevant to the configuration for improving the performance of output voltage accuracy. In the following, the Patent Document 3 is described. Referring to FIG. 18, this DAC is made up by a resistor string, outputting n analog voltages from its respective taps, a first group of switches, made up of n switches of from S1a to Sna, for selecting one voltage V1 from each tap, a second group of switches, made up of n switches of from S1b to Snb, for selecting a voltage V2, neighboring to this voltage V1, a third group of switches, made up of switches SW1, SW2 and SW3, for selecting one of V1 and V2, and an amplifier 200, made up of four differential pairs (Q0A, Q0B), (Q1A, Q1B), (Q2A, Q2B), and (Q3A, Q3B) which are driven by distinct current sources. The output pairs of the four differential pairs are connected in common to input/output pairs of the current mirror circuit (QL1, QL2), while output signals of the four differential pairs are differentially output to a differential amplifier 205, which issues an output voltage Vout at its output terminal. One of inputs of input pairs of the four differential pairs (Q0A, Q0B), (Q1A, Q1B), (Q2A, Q2B), and (Q3A, Q3B) is connected to an output terminal in a feedback configuration. As for the other inputs of the input pairs of the four differential pairs (Q0A, Q0B), (Q1A, Q1B), (Q2A, Q2B), and (Q3A, Q3B), one is connected to the first group of the switches, selecting the voltage V1, with the remaining three being connected to the third group of switches SW1, SW2 and SW3 adapted for selecting one of V1 and V2. Turning to the operation of the DAC, the K'th switches (Ska and Skb) of the first and second group of switches (S1a . . . Sna), (S1b . . . Snb) are turned on by an output of an MSB (Most Significant Bit) subword decoder, based on upper order bit signals of the input data, to select voltages of neighboring taps as V1 and V2, and further the switching of the switches of the third group of switches (SW1, SW2, SW3) is controlled by an output of an LSB (Least Significant Bit) subword decoder, based on lower bit signals of the input data.
By the selecting conditions of the third group of switches (SW1, SW2, SW3), four level voltages Vo1 to Vo4, corresponding to interior division of the voltages V1 and V2, shown in FIG. 19 at different interior division ratios, are output. Specifically,
If the three switches SW1, SW2, SW3 of the third group of switches all select the voltage V1, Vo1 equal to the voltage V1 is output.
If two of the three switches SW1, SW2, SW3 select the voltage V1 and the remaining one selects the voltage V2, Vo2 is output.
If one of the three switches selects the voltage V1 and the remaining two select the voltage V2, Vo3 is output.
If all of the three switches select the voltage V2, Vo4 is output.
If the four level voltages Vo1 to Vo4 are to be output linearly to a high voltage accuracy, it is necessary that the four differential pairs (Q0A, Q0B), (Q1A, Q1B), (Q2A, Q2B), and (Q3A, Q3B) are made up of transistors of the same size, and that the current of the current sources for driving the differential pairs, is controlled to a constant value. By this configuration and switch control, described above, the DAC of FIG. 18 is able to output a sum total of 4n level voltages by the MSB and LSB subwords.
By applying the principle of this DAC to the gray scale voltage generating circuit 983, decoders 984 and to the buffer circuits 985 of FIG. 16, it becomes possible to reduce significantly the number of gray scale voltages output from the gray scale voltage generating circuit 983, to reduce the number of devices for selecting the gray scale voltage and to reduce the circuit scale significantly.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-34234 (FIG. 16)
[Patent Document 2]
U.S. Pat. No. 5,396,245 (FIG. 5)
[Patent Document 3]
U.S. Pat. No. 6,246,351 (FIG. 2)